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ds029 (v1.3) june 25, 2000 www.xilinx.com 2-79 product specification 1-800-255-7778 ? 2000 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. 1 2 3 4 5 6 xq4000x series features certified to mil-prf-38535 appendix a qml (qualified manufacturer listing) ceramic and plastic packages also available under the following standard microcircuit drawings (smd) - xq4013xl 5962-98513 - xq4036xl 5962-98510 - xq4062xl 5962-98511 - xq4085xl 5962-99575 for more information contact the defense supply center columbus (dscc) http://www.dscc.dla.mis/v/va/smd/smdsrch.html available in -3 speed system featured field-programmable gate arrays -selectram ? memory: on-chip ultra-fast ram with synchronous write option dual-port ram option - abundant flip-flops - flexible function generators - dedicated high-speed carry logic - wide edge decoders on each edge - hierarchy of interconnect lines - internal 3-state bus capability - eight global low-skew clock or signal distribution networks system performance beyond 50 mhz flexible array architecture low power segmented routing architecture systems-oriented features - ieee 1149.1-compatible boundary scan logic support - individually programmable output slew rate - programmable input pull-up or pull-down resistors - 12 ma sink current per xq4000xl output configured by loading binary file - unlimited reprogrammability readback capability - program verification - internal node observability development system runs on most common computer platforms - interfaces to popular design environments - fully automatic mapping, placement and routing - interactive design editor for design optimization highest capacity ? over 180,000 usable gates additional routing over xq4000e - almost twice the routing capacity for high-density designs buffered interconnect for maximum speed new latch capability in configurable logic blocks improved versaring ? i/o interconnect for better fixed pinout flexibility - virtually unlimited number of clock signals optional multiplexer or 2-input function generator on device outputs 5v tolerant i/os 0.35 m m sram process introduction the qpro ? xq4000xl series high-performance, high-capacity field programmable gate arrays (fpgas) provide the benefits of custom cmos vlsi, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. the result of thirteen years of fpga design experience and feedback from thousands of customers, these fpgas com- bine architectural versatility, on-chip select-ram memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated soft-ware to achieve fully automated implementation of complex, high-density, high-performance designs. refer to the complete commercial xc4000xl series field programmable gate arrays data sheet for more informa- tion on device architecture and timing, and the latest xilinx databook for package pinouts other than the cb228 (included in this data sheet). (pinouts for xq4000xl device are identical to xc4000xl.) 0 qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 02 product specification r
qpro xq4000xl series qml high-reliability fpgas 2-80 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r table 1: xq4000xl series high reliability field progammable gate arrays device logic cells max logic gates (no ram) (1) max. ram bits (no logic) typical gate range (logic and ram) (1) clb matrix total clbs number of flip-flops max. user i/o packages xq4013xl 2432 13,000 18,432 10,000-30,000 24x24 576 1,536 192 pg223, cb228, pq240, bg256 xq4036xl 3078 36,000 41,472 22,000-65,000 36x36 1,296 3,168 288 pg411, cb228, hq240, bg352 xq4062xl 5472 62,000 73,728 40,000-130,000 48x48 2,304 5,376 384 pg475, cb228, hq240, bg432 xq4085xl 7448 85,000 100,352 55,000-180,000 56x56 3,136 7,168 448 pg475, cb228, hq240, bg432 notes: 1. maximum values of typical gate range includes 20% to 30% of clbs used as ram.
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-81 product specification 1-800-255-7778 r 1 2 3 4 5 6 xq4000xl switching characteristics definition of terms in the following tables, some specifications may be designated as advance or preliminary. these terms are defined as follows: advance: initial estimates based on simulation and/or extrapolation from other speed grades, devices, or devicefamilies. values are subject to change. use as estimates, not for production. preliminary: based on preliminary characterization. further changes are not expected. unmarked: specifications not identified as either advance or preliminary are to be considered final. except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. all specifications are representative of worst-case supply voltage and junction temperature conditions. all specifications subject to change without notice. additional specifications except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. all speci- fications are representative of worst-case supply voltage and junction temperature conditions. the parameters included are common to popular designs and typical appli- cations. for design considerations requiring more detailed timing information, see the appropriate family ac supple- ments available on the xilinx web site at: http://www.xilinx.com/partinfo/databook.htm . absolute maximum ratings (1) recommended operating conditions (1) symbol description units v cc supply voltage relative to gnd ? 0.5 to 4.0 v v in input voltage relative to gnd (2) ? 0.5 to 5.5 v v ts voltage applied to high-z output (2) ? 0.5 to 5.5 v v cct longest supply voltage rise time from 1v to 3v 50 ms t stg storage temperature (ambient) ? 65 to +150 c t sol maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 c t j junction temperature ceramic package +150 c plastic package +125 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. 2. maximum dc overshoot or undershoot above v cc or below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to ? 2.0 v or overshoot to v cc + 2.0v, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. symbol description min max units v cc supply voltage relative to gnd, t j = ? 55 c to +125 cplastic 3.0 3.6 v supply voltage relative to gnd, t c = ? 55 c to +125 c ceramic 3.0 3.6 v v ih high-level input voltage (2) 50% of v cc 5.5 v v il low-level input voltage 0 30% of v cc v t in input signal transition time - 250 ns notes: 1. at junction temperatures above those listed as operating conditions, all delay parameters increase by 0.35% per c. 2. input and output measurement threshold is ~50% of v cc .
qpro xq4000xl series qml high-reliability fpgas 2-82 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r xq4000xl dc characteristics over recommended operating conditions power-on power supply requirements xilinx fpgas require a minimum rated power supply current capacity to insure proper initialization, and the power supply ramp-up time does affect the current required. a fast ramp-up time requires more current than a slow ramp-up time. the slowest ramp-up time is 50 ms. current capacity is not specified for a ramp-up time faster than 2 ms. the cur- rent capacity varies linealy with ramp-up time, e.g. , an xq4036xl with a ramp-up time of 25 ms would require a capacity predicted by the point on the straight line drawn from 1a at 120 m s to 500 ma at 50 ms at the 25 ms time mark. this point is approximately 750 ma . symbol description min max units v oh high-level output voltage at i oh = ? 4 ma, v cc min (lvttl) 2.4 - v high-level output voltage at i oh = ? 500 m a, (lvcmos) 90% v cc -v v ol low-level output voltage at i ol = 12 ma, v cc min (lvttl) (1) -0.4v low-level output voltage at i ol = 1500 m a, (lvcmos) - 10% v cc v v dr data retention supply voltage (below which configuration data may be lost) 2.5 - v i cco quiescent fpga supply current (2) -5ma i l input or output leakage current ? 10 +10 m a c in input capacitance (sample tested) bga, pq, hq, packages - 10 pf pga packages - 16 pf i rpu pad pull-up (when selected) at v in = 0v (sample tested) 0.02 0.25 ma i rpd pad pull-down (when selected) at v in = 3.6v (sample tested) 0.02 0.15 ma i rll horizontal longline pull-up (when selected) at logic low 0.3 2.0 ma notes: 1. with up to 64 pins simultaneously sinking 12 ma. 2. with no output current loads, no active input or longline pull-up resistors, all i/o pins in a high-z state and floating. product description ramp-up time fast (120 m s) slow (50 ms) xq4013 - 36xl minimum required current supply 1a 500 ma xc4062xl minimum required current supply 2a 500 ma xc4085xl (1) minimum required current supply 2a (1) 500 ma notes: 1. the xc4085xl fast ramp-up time is 5 ms. 2. devices are guaranteed to initialize properly with the minimum current listed above. a larger capacity power supply may resul t in a larger initialization current. 3. this specification applies to commercial and industrial grade products only. 4. ramp-up time is measured from 0v dc to 3.6v dc . peak current required lasts less than 3 ms, and occurs near the internal power on reset threshold voltage. after initialization and before configuration, i cc max is less than 10 ma.
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-83 product specification 1-800-255-7778 r 1 2 3 4 5 6 xq4000xl ac switching characteristic testing of the switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. when fewer vertical clock lines are connected, the clock dis- tribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. for more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature) global buffer switching characteristics global early bufges 1, 2, 5, and 6 to iob clock characteristics global early bufges 3, 4, 7, and 8 to iob clock characteristics symbol description device all min -3 -1 units max max t gls delay from pad through global low skew buffer, to any clock k xq4013xl 0.6 3.6 - ns xq4036xl 1.1 4.8 - ns xq4062xl 1.4 6.3 - ns xq4085xl 1.6 - 5.7 ns symbol description device all min -3 -1 units max max t ge delay from pad through global early buffer, to any iob clock. values are for bufges 1, 2, 5 and 6. xq4013xl 0.4 2.4 - ns xq4036xl 0.3 3.1 - ns xq4062xl 0.3 4.9 - ns xq4085xl 0.4 - 4.7 ns symbol description device all min -3 -1 units max max t ge delay from pad through global early buffer, to any iob clock. values are for bufges 3, 4, 7 and 8. xq4013xl 0.7 2.4 - ns xq4036xl 0.9 4.7 - ns xq4062xl 1.2 5.9 - ns xq4085xl 1.3 - 5.5 ns
qpro xq4000xl series qml high-reliability fpgas 2-84 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r xq4000xl clb switching characteristic guidelines testing of switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx develop- ment system) and back-annotated to the simulation netlist. all timing parameters assume worst-case operating condi- tions (supply voltage and junction temperature). values apply to all xq4000xl devices and expressed in nanosec- onds unless otherwise noted. clb switching characteristics symbol description -3 -1 units min max min max combinatorial delays t ilo f/g inputs to x/y outputs - 1.6 - 1.3 ns t iho f/g inputs via h ? to x/y outputs - 2.7 - 2.2 ns t ito f/g inputs via transparent latch to q outputs - 2.9 - 2.2 ns t hh0o c inputs via sr/h0 via h to x/y outputs - 2.5 - 2.0 ns t hh1o c inputs via h1 via h to x/y outputs - 2.4 - 1.9 ns t hh2o c inputs via d in /h2 via h to x/y outputs - 2.5 - 2.0 ns t cbyp c inputs via ec, d in /h2 to yq, xq output (bypass) - 1.5 - 1.1 ns clb fast carry logic t opcy operand inputs (f1, f2, g1, g4) to c out -2.7-2.0ns t ascy add/subtract input (f3) to c out -3.3-2.5ns t incy initialization inputs (f1, f3) to c out -2.0-1.5ns t sum c in through function generators to x/y outputs - 2.8 - 2.4 ns t byp c in to c out , bypass function generators - 0.26 - 0.20 ns t net carry net delay, c out to c in - 0.32 - 0.25 ns sequential delays t cko clock k to flip-flop outputs q - 2.1 - 1.6 ns t cklo clock k to latch outputs q - 2.1 - 1.6 ns setup time before clock k t ick f/g inputs 1.1 - 0.9 - ns t ihck f/g inputs via h 2.2 - 1.7 - ns t hh0ck c inputs via h0 through h 2.0 - 1.6 - ns t hh1ck c inputs via h1 through h 1.9 - 1.4 - ns t hh2ck c inputs via h2 through h 2.0 - 1.6 - ns t dick c inputs via d in 0.9 - 0.7 - ns t ecck c inputs via ec 1.0 - 0.8 - ns t rck c inputs via s/r, going low (inactive) 0.6 - 0.5 - ns t cck c in input via f/g 2.3 - 1.9 - ns t chck c in input via f/g and h 3.4 - 2.7 - ns
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-85 product specification 1-800-255-7778 r 1 2 3 4 5 6 hold time after clock k t cki f/g inputs 0 - 0 - ns t ckih f/g inputs via h 0 - 0 - ns t ckhh0 c inputs via sr/h0 through h 0 - 0 - ns t ckhh1 c inputs via h1 through h 0 - 0 - ns t ckhh2 c inputs via d in /h2 through h 0 - 0 - ns t ckdi c inputs via d in /h2 0 - 0 - ns t ckec c inputs via ec 0 - 0 - ns t ckr c inputs via sr, going low (inactive) 0 - 0 - ns clock t ch clock high time 3.0 - 2.5 - ns t cl clock low time 3.0 - 2.5 - ns set/reset direct t rpw width (high) 3.0 - 2.5 - ns t rio delay from c inputs via s/r, going high to q - 3.7 - 2.8 ns global set/reset t mrw minimum gsr pulse width - 19.8 - 15.0 ns t mrq delay from gsr input to any q see page 95 for t rri values per device. f tog toggle frequency (mhz) (for export control) - 166 - 200 mhz clb switching characteristics (continued) symbol description -3 -1 units min max min max
qpro xq4000xl series qml high-reliability fpgas 2-86 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r xq4000xl ram synchronous (edge-triggered) write operation guidelines testing of switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx develop- ment system) and back-annotated to the simulation netlist. all timing parameters assume worst-case operating condi- tions (supply voltage and junction temperature). values apply to all xq4000xl devices and are expressed in nano- seconds unless otherwise noted. single-port ram synchronous (edge-triggered) write operation characteristics symbol single port ram size -3 -1 units min max min max write operation t wcs address write cycle time (clock k period) 16x2 9.0 - 7.7 - ns t wcts 32x1 9.0 - 7.7 - ns t wps clock k pulse width (active edge) 16x2 4.5 - 3.9 - ns t wpts 32x1 4.5 - 3.9 - ns t ass address setup time before clock k 16x2 2.2 - 1.7 - ns t asts 32x1 2.2 - 1.7 - ns t ahs address hold time after clock k 16x2 0 - 0 - ns t ahts 32x1 0 - 0 - ns t dss d in setup time before clock k 16x2 2.0 - 1.7 - ns t dsts 32x1 2.5 - 2.1 - ns t dhs d in hold time after clock k 16x2 0 - 0 - ns t dhts 32x1 0 - 0 - ns t wss we setup time before clock k 16x2 2.0 - 1.6 - ns t wsts 32x1 1.8 - 1.5 - ns t whs we hold time after clock k 16x2 0 - 0 - ns t whts 32x1 0 - 0 - ns t wos data valid after clock k 16x2 - 6.8 - 5.8 ns t wots 32x1 - 8.1 - 6.9 ns read operation t rc address read cycle time 16x2 4.5 - 2.6 - ns t rct 32x1 6.5 - 3.8 - ns t ilo data valid after address change (no write enable) 16x2 - 1.6 - 1.3 ns t iho 32x1 - 2.7 - 2.2 ns t ick address setup time before clock k 16x2 1.1 - 0.9 - ns t ihck 32x1 2.2 - 1.7 - ns
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-87 product specification 1-800-255-7778 r 1 2 3 4 5 6 dual-port ram synchronous (edge-triggered) write operation characteristics symbol dual port ram size (1) -3 -1 units min max min max write operation t wcds address write cycle time (clock k period) 16x1 9.0 7.7 ns t wpds clock k pulse width (active edge) 16x1 4.5 - 3.9 - ns t asds address setup time before clock k 16x1 2.5 - 1.7 - ns t ahds address hold time after clock k 16x1 0 - 0 - ns t dsds d in setup time before clock k 16x1 2.5 - 2.0 - ns t dhds d in hold time after clock k 16x1 0 - 0 - ns t wsds we setup time before clock k 16x1 1.8 - 1.6 - ns t whds we hold time after clock k 16x1 0 - 0 - ns t wods data valid after clock k 16x1 - 7.8 - 6.7 ns
qpro xq4000xl series qml high-reliability fpgas 2-88 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r x q 4000xl clb si ngle-port r a m s y n c h r o n ous (ed g e- t r i g g e red) write ti m i ng xq4000xl clb dual-port ram synchronous (edge-triggered) write timing ds029_01_011300 wclk (k) we address data in d ata out old new t dss t dhs t ass t ahs t wss t wps t whs t wos t ilo t ilo ds029_02_011300 wclk (k) we address data in data out old new t dsds t dhds t asds t ahds t wss t wpds t whs t wods t ilo t ilo
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-89 product specification 1-800-255-7778 r 1 2 3 4 5 6 xq4000xl pin-to-pin output parameter guidelines testing of switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing ana- lyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values are expressed in nanosec- onds unless otherwise noted. output flip-flop, clock to out (1,2,3) output flip-flop, clock to out, bufges 1, 2, 5, and 6 symbol description device all min -3 -1 units max max t ickof global low skew clock to output using off (4) xq4013xl 1.5 8.6 - ns xq4036xl 2.0 9.8 - ns xq4062xl 2.3 11.3 - ns xq4085xl 2.5 - 9.5 ns t slow for output slow option add all devices 3.0 3.0 3.0 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. clock-to-out minimum delay is measured with the fastest route and the lightest load, clock-to-out maximum delay is measured u sing the farthest distance and a reference load of one clock pin (ik or ok) per iob as well as driving all accessible clb flip-flops . for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be added to the ac parameter tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for fast mode configurations. 3. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. 4. off = output flip-flop symbol description device all min -3 -1 units max max t ickeof global early clock to output using off values are for bufges 1, 2, 5, and 6. xq4013xl 1.3 7.4 - ns xq4036xl 1.2 8.1 - ns xq4062xl 1.2 9.9 - ns xq4085xl 1.3 - 8.5 ns notes: 1. clock-to-out minimum delay is measured with the fastest route and the lightest load, clock-to-out maximum delay is measured u sing the farthest distance and a reference load of one clock pin (ik or ok) per iob as well as driving all accessible clb flip-flops . for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be added to the ac parameter tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for fast mode configurations. 2. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load.
qpro xq4000xl series qml high-reliability fpgas 2-90 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r output flip-flop, clock to out, bufges 3, 4, 7, and 8 capacitive load factor figure 1 shows the relationship between i/o output delay and load capacitance. it allows a user to adjust the specified output delay if the load capacitance is different than 50 pf. for example, if the actual load capacitance is 120 pf, add 2.5 ns to the specified delay. if the load capacitance is 20 pf, subtract 0.8 ns from the specified output delay. figure 1 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control. symbol description device all min -3 -1 units max max t ickeof global early clock to output using off values are for bufges 3, 4, 7, and 8. xq4013xl 1.8 8.8 - ns xq4036xl 1.8 9.7 - ns xq4062xl 2.0 10.9 - ns xq4085xl 2.2 - 9.3 ns notes: 1. clock-to-out minimum delay is measured with the fastest route and the lightest load, clock-to-out maximum delay is measured u sing the farthest distance and a reference load of one clock pin (ik or ok) per iob as well as driving all accessible clb flip-flops . for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be added to the ac parameter tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for fast mode configurations. 2. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. figure 1: delay factor at various capacitive loads ds029_03_011300 -2 0 20406080 capacitance (pf) delta delay (ns) 100 120 140 -1 0 1 2 3
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-91 product specification 1-800-255-7778 r 1 2 3 4 5 6 xq4000xl pin-to-pin input parameter guidelines testing of switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing ana- lyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values are expressed in nanosec- onds unless otherwise noted. global low skew clock, input setup and hold times (1,2) symbol description device (1) -3 -1 units min min no delay t psn /t phn global early clock and iff (3) global early clock and fcl (4) xq4013xl 1.2 / 3.2 - ns xq4036xl 1.2 / 5.5 - ns xq4062xl 1.2 / 7.0 - ns xq4085xl - 0.9 / 7.1 ns partial delay t psp /t php global early clock and iff (3) global early clock and fcl (4) xq4013xl 6.1 / 0.0 - ns xq4036xl 6.4 / 1.0 - ns xq4062xl 6.7 / 1.2 - ns xq4085xl - 9.8 / 1.2 ns full delay t psd /t phd global early clock and iff (3) xq4013xl 6.4 / 0.0 - ns xq4036xl 6.6 / 0.0 - ns xq4062xl 6.8 / 0.0 - ns xq4085xl - 9.6 / 0.0 ns notes: 1. the xq4013xl, xq4036xl, and xq4062xl have significantly faster partial and full delay setup times than other devices. 2. input setup time is measured with the fastest route and the lightest load. input hold time is measured using the furthest dis tance and a reference load of one clock pin per iob as well as driving all accessible clb flip-flops. for designs with a smaller number o f clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be used as a worst-case pin-to-pin no-delay input hold specification. 3. iff = input flip-flop or latch 4. fcl = fast capture latch
qpro xq4000xl series qml high-reliability fpgas 2-92 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r global early clock bufes 1, 2, 5, and 6 setup and hold for iff and fcl (1,2) symbol description device -3 -1 min min no delay t psen /t phen t pfsen /t pfhen global early clock and iff (3) global early clock and fcl (4) xq4013xl 1.2 / 4.7 - xq4036xl 1.2 / 6.7 - xq4062xl 1.2 / 8.4 - xq4085xl - 0.9 / 6.6 partial delay t psepn /t phep t pfsep /t pfhep global early clock and iff (3) global early clock and fcl (4) xq4013xl 6.4 / 0.0 - xq4036xl 7.0 / 0.8 - xq4062xl 9.0 / 0.8 - xq4085xl - 11.0 / 0.0 full delay t psepd /t phed global early clock and iff (3) xq4013xl 12.0 / 0.0 - xq4036xl 13.8 / 0.0 - xq4062xl 13.1 / 0.0 - xq4085xl - 13.6 / 0.0 notes: 1. the xq4013xl, xq4036xl, and xq4062xl have significantly faster partial and full delay setup times than other devices. 2. input setup time is measured with the fastest route and the lightest load. input hold time is measured using the furthest dis tance and a reference load of one clock pin per iob as well as driving all accessible clb flip-flops. for designs with a smaller number o f clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be used as a worst-case pin-to-pin no-delay input hold specification. 3. iff = input flip-flop or latch 4. fcl = fast capture latch
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-93 product specification 1-800-255-7778 r 1 2 3 4 5 6 global early clock bufes 3, 4, 7, and 8 setup and hold for iff and fcl (1,2) symbol description device -3 -1 min min no delay t psen /t phen t pfsen /t pfhen global early clock and iff (3) global early clock and fcl (4) xq4013xl 1.2 / 4.7 - xq4036xl 1.2 / 6.7 - xq4062xl 1.2 / 8.4 - xq4085xl - 0.9 / 6.6 partial delay t psepn /t phep t pfsep /t pfhep global early clock and iff (3) global early clock and fcl (4) xq4013xl 5.4 / 0.0 - xq4036xl 6.4 / 0.8 - xq4062xl 8.4 / 1.5 - xq4085xl - 11.0 / 0.0 full delay t psepd /t phed global early clock and iff (3) xq4013xl 10.0 / 0.0 - xq4036xl 12.2 / 0.0 - xq4062xl 13.1 / 0.0 - xq4085xl - 13.6 / 0.0 notes: 1. the xq4013xl, xq4036xl, and xq4062xl have significantly faster partial and full delay setup times than other devices. 2. input setup time is measured with the fastest route and the lightest load. input hold time is measured using the furthest dis tance and a reference load of one clock pin per iob as well as driving all accessible clb flip-flops. for designs with a smaller number o f clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be used as a worst-case pin-to-pin no-delay input hold specification. 3. iff = input flip-flop or latch 4. fcl = fast capture latch
qpro xq4000xl series qml high-reliability fpgas 2-94 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r xq4000xl iob input switching characteristic guidelines testing of switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx develop- ment system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (sup- ply voltage and junction temperature) . symbol description device -3 -1 units min max min max clocks t ecik clock enable (ec) to clock (ik) all devices 0.1 - 0.1 - ns t okik delay from fcl enable (ok) active edge to iff clock (ik) active edge all devices 2.2 - 1.6 - ns setup times t pick pad to clock (ik), no delay all devices 1.7 - 1.3 - ns t pickf pad to clock (ik), via transparent fast capture latch, no delay all devices 2.3 - 1.8 - ns t pock pad to fast capture latch enable (ok), no delay all devices 1.2 - 0.9 - ns hold times all hold times all devices 0 - 0 - ns global set/reset t mrw minimum gsr pulse width all devices - 19.8 - 15.0 ns t rri delay from gsr input to any q (2) xq4013xl - 15.9 - - ns xq4036xl - 22.5 - - ns xq4062xl - 29.1 - - ns xq4085xl - - - 26.0 ns propagation delays t pid pad to i1, i2 all devices - 1.6 - 1.7 ns t pli pad to i1, i2 via transparent input latch, no delay all devices - 3.1 - 2.4 ns t pfli pad to i1, i2 via transparent fcl and input latch, no delay all devices - 3.7 - 2.8 ns t ikri clock (ik) to i1, i2 (flip-flop) all devices - 1.7 - 1.3 ns t ikli clock (ik) to i1, i2 (latch enable, active low) all devices - 1.8 - 1.4 ns t okli fcl enable (ok) active edge to i1, i2 (via transparent standard input latch) all devices - 3.6 - 2.7 ns notes: 1. iff = input flip-flop or latch, fcl = fast capture latch 2. indicates minimum amount of time to assure valid data.
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-95 product specification 1-800-255-7778 r 1 2 3 4 5 6 xq4000xl iob output switching characteristic guidelines testing of switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx develop- ment system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (sup- ply voltage and junction temperature). for propagation delays, slew-rate = fast unless otherwise noted. values are expressed in nanoseconds unless otherwise noted. symbol description -3 -1 units min max min max clocks t ch clock high 3.0 - 2.5 - ns t cl clock low 3.0 - 2.5 - ns propagation delays t okpof clock (ok) to pad - 5.0 - 3.8 ns t opf output (o) to pad - 4.1 - 3.1 ns t tshz high-z to pad high-z (slew-rate independent) - 4.4 - 3.0 ns t tsonf high-z to pad active and valid - 4.1 - 3.3 ns t ofpf output (o) to pad via fast output mux - 5.5 - 4.2 ns t okfpf select (ok) to pad via fast mux - 5.1 - 3.9 ns setup and hold times t ook output (o) to clock (ok) setup time 0.5 - 0.3 - ns t oko output (o) to clock (ok) hold time 0 - 0 - ns t ecok clock enable (ec) to clock (ok) setup time 0 - 0 - ns t okec clock enable (ec) to clock (ok) hold time 0.3 - 0.1 - ns global set/reset t mrw minimum gsr pulse width 19.8 - 15.0 - ns t rpo delay from gsr input to any pad (2) xq4013xl - 20.5 - - ns xq4036xl - 27.1 - - ns xq4062xl - 33.7 - - ns xq4085xl - - 29.5 ns slew rate adjustment t slow for output slow option add - 3.0 - 2.0 ns notes: 1. output timing is measured at ~50% v cc threshold, with 50 pf external capacitive loads. 2. indicates minimum amount of time to assure valid data.
qpro xq4000xl series qml high-reliability fpgas 2-96 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r cb228 pinouts table 2: cb228 package pinouts pin name cb228 vtt gnd p1 bufgp_tl_a16_gck1_io p2 a17_io p3 io p4 io p5 tdi_io p6 tck_io p7 io p8 io p9 io p10 io p11 io p12 io p13 gnd p14 io_fclk1 p15 io p16 tms_io p17 io p18 io p19 io p20 io p21 io p22 io p23 io p24 io p25 io p26 gnd p27 v cc p28 io p29 io p30 io p31 io p32 io p33 io p34 io p35 io p36 v cc p37 io p38 io p39 io p40 io_fclk2 p41 gnd p42 io p43 io p44 io p45 io p46 io p47 io p48 io p49 io p50 io p51 io p52 io p53 bufgs_bl_gck2_io p54 m1 p55 gnd p56 m0 p57 v cc p58 m2 p59 bufgp_bl_gck3_io p60 hdc_io p61 io p62 io p63 io p64 ldc_io p65 io p66 io p67 io p68 io p69 io p70 io p71 gnd p72 io p73 io p74 io p75 io p76 io p77 io p78 ta b l e 2 : cb228 package pinouts (continued) pin name cb228
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-97 product specification 1-800-255-7778 r 1 2 3 4 5 6 io p79 io p80 io p81 io p82 io p83 /err_init_io p84 v cc p85 gnd p86 io p87 io p88 io p89 io p90 io p91 io p92 io p93 io p94 v cc p95 io p96 io p97 io p98 io p99 gnd p100 io p101 io p102 io p103 io p104 io p105 io p106 io p107 io p108 io p109 io p110 io p111 bufgs_br_gck4_io p112 gnd p113 done p114 v cc p115 /program p116 d7_io p117 bufgp_br_gck5_io p118 table 2: cb228 package pinouts (continued) pin name cb228 io p119 io p120 io p121 io p122 d6_io p123 io p124 io p125 io p126 io p127 io p128 gnd p129 io p130 io p131 io_fclk3 p132 io p133 d5_io p134 /cs0_io p135 io p136 io p137 io p138 io p139 d4_io p140 io p141 v cc p142 gnd p143 d3_io p144 /rs_io p145 io p146 io p147 io p148 io p149 d2_io p150 io p151 v cc p152 io p153 io_fclk4 p154 io p155 io p156 gnd p157 io p158 ta b l e 2 : cb228 package pinouts (continued) pin name cb228
qpro xq4000xl series qml high-reliability fpgas 2-98 www.xilinx.com ds029 (v1.3) june 25, 2000 1-800-255-7778 product specification r io p159 io p160 io p161 io p162 io p163 d1_io p164 busy_/rdy_rclk_io p165 io p166 io p167 d0_din_io p168 bufgs_tr_gck6_dout_io p169 cclk p170 v cc p171 tdo p172 gnd p173 a0_/ws_io p174 bufgp_tr_gck7_a1_io p175 io p176 io p177 csi_a2_io p178 a3_io p179 io p180 io p181 io p182 io p183 io p184 io p185 gnd p186 io p187 io p188 io p189 io p190 v cc p191 a4_io p192 a5_io p193 io p194 io p195 a21_io p196 a20_io p197 a6_io p198 table 2: cb228 package pinouts (continued) pin name cb228 a7_io p199 gnd p200 v cc p201 a8_io p202 a9_io p203 a19_io p204 a18_io p205 io p206 io p207 a10_io p208 a11_io p209 v cc p210 io p211 io p212 io p213 io p214 gnd p215 io p216 io p217 io p218 io p219 a12_io p220 a13_io p221 io p222 io p223 io p224 io p225 a14_io p226 bufgs_tl_gck8_a15_io p227 v cc p228 ta b l e 2 : cb228 package pinouts (continued) pin name cb228
qpro xq4000xl series qml high-reliability fpgas ds029 (v1.3) june 25, 2000 www.xilinx.com 2-99 product specification 1-800-255-7778 r 1 2 3 4 5 6 ordering information revision history the following table shows the revision history for this document device type xq4085xl xq4062xl xq4036xl xq4013xl package type cb = top brazed ceramic quad flat pack pg = ceramic pin grid array pq/hq = plastic quad flat back bg = plastic ball grid array temperature range m = military ceramic (t c = ? 55 o c to +125 o c) n = military plastic (t j = ? 55 c to +125 c) mil-prf-38535 (qml) processed number of pins xq 4062xl -3 pg 475 m example for qpro ? military temperature part : speed grade -3 -1 (xq4085xl only) date version description 05/01/98 1.0 original document release. 01/01/99 1.1 addition of new packages, clarification of parameters. 02/09/00 1.2 addition of xq4085xl-1 speed grade part. 06/25/00 1.3 updated timing specifications to match with commercial data sheet. updated format. device type xq4013xl = 98513 xq4036xl = 98510 xq4062xl = 98511 xq4085xl = 99575 package type x = pin grid y = ceramic quad flat pack (base mark) z = ceramic quad flat pack (lid mark) t = plastic quad flat pack u = plastic ball grid lead finish c = gold b = solder generic standard microcircuit drawing (smd) prefix 5962 98511 01 q x c q = qml certified n = qml plastic (n - grade) example for smd part : speed grade 01 = -3 for xq4103xl/4036xl/4062xl 01 = -1 for xq4085xl

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